FIG. 1 shows a basic instruction execution pipeline 100. The basic instruction execution pipeline is observed to include: i) an instruction fetch stage 101; ii) a data fetch stage 102; iii) an instruction execution stage 103; and, iv) a write back stage 104. The instruction fetch stage 101 fetches “next” instructions in an instruction sequence from a cache, or, system memory (if the desired instructions are not within the cache). Instructions typically specify operand data and an operation to be performed on the operand data. The data fetch stage 102 fetches the operand data from local operand register space, a data cache or system memory. The instruction execution stage 103 performs the operation called out by an instruction on the operand data that is specified by the instruction and fetched by the data fetch stage 102. The write back stage “retires” the result of the execution, typically by writing the result into local register space.